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Job Title :Analog Design Engineer/ e: M. b1 g9 x* Q5 ^7 l
Job Category :Semiconductor
' a, C5 `: C9 wLocation : Malaysia
3 a) g9 |0 l( ]' o! f8 dJob Type : Permanent9 G- B6 N& Y# r" X
Job Description:
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Analog IC Designer to for all technical aspects of design from feasibility to specification to monitoring layout of the design, tapeout and silicon validation.
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Responsibilities:
. q9 w8 A+ m% zInteraction with customer to understand customer requirements, develop product specification and to provide technical support.# m) Z- ?- \5 U7 K$ j5 K' i8 f
Close interaction with the design team.4 w/ s) S5 s# d+ T6 ~2 U v- W
Support and guide the layout team. Proper documentation will have to be provided throughout including a detailed test plan for the validation of the design/IP.
! p. u: P0 p4 nMaintain proper documentation throughout projects including a detailed test plan for the validation of the design/IP.
x. J% V2 O' N( U2 [) T3 l7 w: uRequirements:0 N* B. i; g- `/ m
In-depth understanding of leading process technologies such as sub-micron CMOS/BiCMOS/DMOS, BCD, HV
& L6 J5 G- j% @+ K2 {, @Experience with simulation tools required to efficiently simulate analog/mixed-signal circuits e.g. Spectre, Ultrasim, HSpice etc2 S- G) z& |' z% i7 Z
Understanding of simulation models, design rules and verification procedures (DRC/LVS/ERC) is essential.
8 z+ t" B, s4 G K' u4 BDetailed knowledge in the design and operation of the following analog blocks:3 s4 h1 h0 L" N% _4 U, A! E: C* v
- Basic analog building blocks (op amps, comparators, current sources, current mirrors, voltage references)% {7 f% M, J1 B4 }
- Power management blocks (bandgap references, linear regulators, DC-DC converter of various topologies, LDOs)# e% S2 K! m5 M' o) A
- System level protection blocks (UVLO, POR, OTP, Short circuit protection etc)- o2 G1 N7 r" N- ]9 d- `
- PLL and transceiver blocks (output drivers, multiplexer and de-multiplexer, clock generator, equalizers, clock and data recovery, frequency detectors, oscillators, filters)! ]/ z+ G4 C3 J
- ADCs and DACs& _" h4 f4 C$ ^, t9 S2 o+ o
Experience with design practices such as minimizing device mismatch, noise, signal coupling, ESD, latchup and device SOA is a must./ P* ?% j" ~2 o/ ^8 j
Modelling and design skills in Verilog-A/Verilog-AMS and system modelling with Matlab is an added advantage. i6 R) I# C1 \+ d2 N9 J
A track record as a team player and capable of leading teams C. S1 ~( {, \0 T4 v6 h& o, _
Proven experience in developing and meeting engineering schedules" ] ~6 `; s9 L
Strong analytical skills
- E& R8 z7 D* o+ BStrong organizational, interpersonal, written and verbal communication skills. |
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