[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
ABT={2'b00, DATA, 4'b0000};
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" ^/ H9 z/ E  W( T# _/ J! HVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
- w, p) b3 P& I– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
0 I( {9 d9 V+ ~. w5 P* n7 o– Logical shift operators: >>, <<
– Conditional operators: ? :
+ v$ y: U& _' {/ i0 f' U5 G) R/ q( U– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
給你參考一下