[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
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" \+ m, k' V' \# j/ J3 ^3 V, s% BVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
1 V; [5 ]) I$ U6 _; k: ]– Relational operators: >, <, >=, <=, ==, !=, ===, !==
1 z7 Q& Q. e* B5 o* R: Z+ ]- v3 |0 ?( e– Logical shift operators: >>, <<
! C, a/ B4 w( B# H+ V– Conditional operators: ? :
– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
給你參考一下