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【工作內容】
) \0 H5 K9 R2 m先進製程與模組開發 (DRAM/ Flash/ Logic)
8 w0 u2 l3 k, K$ o$ Z1 d* y- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),# b! B% N, n, Z) t0 x) E0 h
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
( Z( g* | I6 _0 a$ ^5 w Metrology & Inspection, etc." I7 F: n/ I) O; [- ~% m
- Device Isolation, Transistor, Capacitor, Dielectric! I- u& ^4 H" T
- High-K/Metal Gate, SiO2/SiON Gate Dielectric
. T5 b$ ^! k& L& G0 X- Low-K, Interconnect, etc.$ C6 t+ f5 t ]- ^
※ OPC: Optical Proximity Correction (Comput. Litho)
/ n/ t8 N' X7 ~, s' d MPC: Mask Process Correction- F: i: C3 |" r1 [! K& u
0 @5 K# w; d2 f' X2 @FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)+ w5 R6 P5 ^2 J; D/ r
新型記憶體: PRAM, STT-MRAM, ReRAM
7 M! y$ W9 `$ H8 `( `, n+ rTCAD/ECAD9 h1 z5 h4 i$ f; V* o
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling
2 Y4 W$ O, Z( ]- Circuit Simulator Development0 x# ]8 U0 M A. D" P, {0 ^
- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design( k! t5 F" ^; @/ k7 B
- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/1 B' W8 w0 T4 h* l+ v# ]" G2 v
SSD Research Experience |
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