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各位:现做mixed-signal仿真,使用的工具为spectreverilog,随便做一一个电路,现在报以下错误,不知道是怎么回事,望各位指点:* r! f* t9 c, T0 b! b! l2 F2 I5 A
该错误是在做以下操作时显示:Mixed-signal/Display Partition/All Active
3 Z5 s! \) b4 R! }: `; c% u( \9 z0 ferror: failed to partition the design.# D( C3 E0 D5 P, P
......unsuccessful.
" r( h5 {. t4 Kerror: cannot create and partition the design.
% {9 A9 g& E- J% K6 c: M! Q7 perror: must fix design errors before netlisting.0 l" h! Z$ E2 `. t9 u7 @
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PS:在做混合信号仿真时,需要注意些什么?有什么比较实用的资料可以参考,多谢! |
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