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Device development engineer' T3 c \# ]+ R* I$ P# e
6 `/ E3 v) d, f% B% L* J. @! z公 司:A famous IC company
9 [$ E+ E5 d9 \6 @; i: o2 B! T9 _工作地点:上海( j1 F& j7 n* G) ~ E( @
9 [1 X' {% |: R! V, Y9 k9 FDuties
0 a4 I4 z9 a! W· Facilitate product design work in foundry process(LG, MS and BCD process).
/ Y/ b3 i/ `/ \: l" b/ H· Have a strong device/process background for 90nm~0.18um logic process, mixed-signal, embedded FLASH memory, and BCD process. 5 ^8 S8 O" j( P! {8 ]
· Tasks would include answering device and process related questions, interpreting DRC and LVS results, helping with tapeout and mask ordering, doing jobview mask inspections, and also participate the process/device development projects.
7 L# |4 p! @" T1 |! _. N; Q9 D" i· Would be expected to establish relationships with his technical peers at foundries and discuss important technical issues with them on an almost daily basis. 5 Q- R2 N1 P4 h: y8 G
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Requirements
$ ]$ T! u3 E4 S! g( @0 k) }. x0 m· Senior level engineer (minimum 8 years experience with BSEE or minimum 5 years experience with MSEE or PhD)
/ f t l7 B, E8 p G· Excellent device knowledge (LV CMOS, BJT, BCD, embedded FLASH memory, OTP/MTP, latchup, ESD, device reliability) / }9 Q/ c/ [. A
· Excellent to very good knowledge of PDK systems (design rule, verification software, mask ordering, device pcells, circuit modeling, parasitic parameter extraction, and so on)
+ P& v$ O- _+ `) M" q7 F6 e· Some knowledge of circuit design, primarily from a device usage standpoint.
! l y* q" p4 {0 p6 T· Knowledge of major Asian foundry systems, process technologies, and devices would be a positive.
J7 u4 b+ F6 n8 Y# S· Ability to understand and solved technical problems relating to semiconductor devices with a minimal amount of guidance.
$ O, ^$ f! b. o5 b5 p* M- g· Excellent people/communication skills |
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