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徵求記憶體6-bit data in 64個字組,不過不要用陣列的方式,很感謝大家提共意見,不過都不是實際記憶體電路的VHDL,我想要的是一個column decoder,一個row decorder,使用port map latch 64個,輸出要使用三態閘,個人想法如下:2 g& k6 o: _) s1 p
LIBRARY ieee;
7 E1 {2 m+ q* D5 @" v$ LUSE ieee.std_logic_1164.all;
; `! P4 B9 w/ c' ~. o) @' [USE ieee.std_logic_arith.all;
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ENTITY memory_64 IS: r' ?( Z1 B# i3 D* q
PORT( 5 y# v& c! ^1 X1 I5 {( W
mem_in : IN std_logic_vector ( 5 DOWNTO 0 );# y8 s* W# {! O5 m0 w/ x
mem_out : OUT std_logic_vector ( 5 DOWNTO 0 );4 h! O' ^6 H' O1 R
clr_l : IN std_logic;) @' t* A. N5 O7 \' M
mem_addr : IN std_logic_vector ( 5 DOWNTO 0 )' Y/ ^' E' ~3 `
);. P: E0 |( c# _$ s
1 R/ z. T& X( d6 g; G% p( c$ I& t-- Declarations
+ F- _1 l( K9 x# {
( x5 n# C2 K9 y6 H/ xEND memory_64 ;- O3 v3 |9 L3 ?/ C! @2 d6 }" e
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--/ G# N' l+ ^3 g& M
ARCHITECTURE arch OF memory_64 IS" P. i% k- o X, m* N- q* H7 y+ S; R2 `
-- column decoder
& o& }9 J5 t& @/ e+ r+ Ycomponent mem_coldec$ C, q! ~" o7 n, Z9 X) e* w* s3 C0 }5 Q
PORT( , M h+ M# Y7 R3 L3 A; E8 k
col_addr : IN std_logic_vector ( 2 DOWNTO 0 );+ Z1 n; F/ N! k {7 ]. l' \ z" I& ]
col_sel : OUT std_logic_vector ( 7 DOWNTO 0 )0 Q$ r; |( O- g. Q0 j
);
/ x; J+ B7 Q# \4 z) M4 iend component;
. ]' a" B5 [5 @-- row decoder0 r- ?2 Y. D8 w0 E7 t
component mem_rowdec" x7 f& n0 P* _2 J, q
PORT( ( b* M" {0 V7 h$ Y
row_addr : IN std_logic_vector ( 2 DOWNTO 0 );% L5 b6 E e i( t$ P3 T
row_sel : OUT std_logic_vector ( 7 DOWNTO 0 )
" y b \" f2 c- b: Y5 _/ v3 g );
8 B% F% g1 w: Q* ]" Mend component;
5 M$ s* J& n# a# [* R0 |+ @! I-- latch array
I2 [/ L# E: I' L6 Jcomponent latch_cell8 H) r6 o5 S: y7 o1 A5 w
PORT(
9 h; B! w* l, ^# S clr_l : IN std_logic;+ F) ^, ]+ }. T4 y8 C/ ~
col_sel : IN std_logic;
5 d. ~- E1 o, \ row_sel : IN std_logic; ! v6 y) V R0 |" h, e
data_in : IN std_logic_vector ( 5 DOWNTO 0 );
2 v# ]% S, Q; F, a! Y data_out : OUT std_logic_vector ( 5 DOWNTO 0 ), i8 F9 f/ @$ N* y
);
1 X Q# h4 t4 E5 A) v7 hend component; ; ?% ]3 S1 @8 E P s6 p- s
5 N) w3 J# r. Q" ] {. v% `signal smem_out : std_logic_vector ( 5 downto 0 );
( `- s0 U1 Y. W/ N6 J5 M* L% L, hsignal scol_sel,srow_sel : std_logic_vector( 7 downto 0 ); W" d6 D- C6 m
BEGIN/ g! i; \9 d& E& J& Y4 p% v8 \; [
u_0 : mem_coldec port map(mem_addr( 5 downto 3 ),scol_sel);
+ X+ y" K0 [1 Y: x9 d# ?/ v; l u_1 : mem_rowdec port map(mem_addr( 2 downto 0 ),srow_sel);, `3 T5 x5 o! \3 ?7 C$ r' h
g0 : for i in 7 downto 0 generate -- column generate! M1 L) ] x6 \: s5 S% I( T0 B
g1 : for j in 7 downto 0 generate -- row generate
! F# N+ H1 W% r! C ~7 r u_2 : latch_cell
3 g+ @ j- B R port map(, x7 ~, x4 w6 u- Q5 G1 Y8 \
col_sel => col_sel(j),! }0 z" M1 k: l& e8 B
row_sel => srow_sel(i),
% N% W! C* A0 w% W data_in => mem_in,
, d4 S: q4 Z; F data_out => mem_out(i)( s+ S- T. I3 p4 A" |3 Q
);4 F" O, H H& r
end generate;
' N; G9 i. f2 u9 y. a. x end generate;2 H% ]: ~" T- d2 w. \: m1 @) V
END ARCHITECTURE arch;/ _/ Z/ u# I" X9 s. ]( Z9 G3 d
不過模擬很久,始終沒辦法寫進我想要寫的位址,試寫了很久,但是始終寫不出來,所以請大家幫個忙,不然那些範例網路上都有,有點急,請大家廣發建議,感謝大家! |
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