Calibration techniques in nyquist AD converters

cnasic

Table of contents
List of abbreviations
List of symbols
2 I* \7 |/ }- Z/ Y6 _! uPreface
/ s6 M# j; I0 P; x7 P1 Introduction 1
( B7 d. z, G) i- b5 B0 [, [1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
3 F$ X) o' h* c% n$ G3 E" b9 u1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 ]* S2 }4 _/ f, `! o2 Accuracy, speed and power relation 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
4 n1 n! u! G2 K: t+ ~5 S1 [2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 . . . . . . . . . . . . . . . . . . . . . 15
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 A/D converter architecture comparison 21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
" @; @/ U) a4 O6 B, V" P" ^3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
% @5 }% h8 y+ g3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
: P4 k7 T! Y  L( g6 [; R3 ]CMOS technology trends
2 _( T' N4 U5 J7 n6 u* W1 |xi
9 W- t+ ^1 E% ?) \9 y. G1 w0 I. v" |xiii
xvii
Table of contents
6 d, y) \" B; _+ y3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
( u# k0 `9 k  J1 ^& q2 |3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
/ B( b, [+ _0 z3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
4 R! N0 O3 \6 D' V& L3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
! t" \  D2 a7 G: u; S3 L; r1 F3.7.2 Architecture comparison as a function of the resolution . . 57
7 m! w6 s% R4 V( V: g3.7.3 Architecture comparison as a function of the sampling speed 65
4 z7 p& l* \+ |" A. h$ X3 d% `1 ~3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8 N* I7 ]' `1 X9 `$ D4 Enhancement techniques for two-step A/D converters 67
% K& ^0 Z* n0 @5 l* j& ]& r4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
: p* |  G; r" Y1 n6 D/ @4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
8 |" W6 z' a0 M, g4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
  R& u+ J5 i" X: {8 K, ~4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
! H/ x# B/ p# q5 L7 R4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
& u2 B5 S  b1 g, @' V# o4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
( Y2 q  i! {$ @2 O2 k6 B4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
3 r6 x" M. ^4 f4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
4.5.4 Offset extraction and analog compensation . . . . . . . . 91
8 c& c) Z: M4 K  d; ]$ ^$ c4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
" s* I% b* K. g; o/ T5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
* O. }/ c$ N- A5.2
1 G! @0 [+ @0 M4 a5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
2 g5 Z% X( Y+ |4 j4 ~" ^% h- j9 U2 V6 P5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
/ |! B1 a: N8 H9 g) D% t1 {5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
5 m% c7 |# _& k( I* _) f5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
. y9 \( z& ^' y' s, N5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
% x2 a3 u* y7 `5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
6 ?' h  n4 c4 V3 N" \& z5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
) r6 @1 L/ e7 o% H0 a! I5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
, _% s4 H2 h0 o4 x8 U5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
, H5 T+ Y* ~# m; l& k5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5 s' G/ D' j9 k7 b$ ]viii
, J5 g+ j1 o% v# D$ W* J" }Two-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
: Y3 l' k. A( qTable of contents
+ v+ ^# G# w* o5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
) H' c2 l2 y9 V0 w2 ~5 G  W# s2 O8 c5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2 ~" n& |( {0 x+ s. t' W& L6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
7 A low-power 16-bit three-step ADC for imaging applications 149

xp212125o

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tuza2000

good material !!!