Calibration techniques in nyquist AD converters

cnasic

Table of contents
) G+ K8 z, T9 C4 w1 f4 B0 p% JList of abbreviations
  L1 O* _. u8 ]( ^6 H) S$ U. {List of symbols
Preface
1 Introduction 1
1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
) M1 s* ~9 T5 l! {4 y1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
, `9 \( V2 R0 N- P5 h3 t1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Accuracy, speed and power relation 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 W7 ^( n6 `" T$ H2 z2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
8 X- J0 S$ I/ B2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
& D" w3 _1 c( Q2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
* }9 \' ]' d8 g6 N9 n2.5 . . . . . . . . . . . . . . . . . . . . . 15
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
: V) t: Q0 Q: {4 s3 A/D converter architecture comparison 21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 T- b: V' p0 x3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
% ]1 v6 B. u  u3 i; f) |* E: i2 P3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
$ X* I) L1 Y% Y. R3 |3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 V& y0 _( J) h/ B$ A2 lThermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
' a# k- S3 l4 [- P+ o5 G# P9 NCMOS technology trends
# ?# t" A4 r* n, R6 fxi
xiii
- K6 Z# R( Q& v  f, U  w* Z2 Qxvii
6 H8 @" m5 t6 M8 {/ iTable of contents
: }, w  A" A* A; G- I5 F3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
, f" h8 E2 W! g8 O8 a3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
6 o3 X1 [$ C  m% y/ U3 |3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
3.7.2 Architecture comparison as a function of the resolution . . 57
3.7.3 Architecture comparison as a function of the sampling speed 65
3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 S, Y7 d1 [8 T1 p: a# Z4 Enhancement techniques for two-step A/D converters 67
: V! D' r$ X# f3 b5 U3 Z4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
4 h* Q3 y/ T+ N! }$ t4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3 t8 y, {, H. L4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
6 i: f; A" W1 ^+ Q4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
  e$ S- d' b8 B' Q8 ?4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
4.5.4 Offset extraction and analog compensation . . . . . . . . 91
4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8 C& h% u+ o7 |- \/ e( j5.2
5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
( ?9 R2 B. n9 T# R( o5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
& l/ X* W" N5 h5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3 v1 w* B: |+ d% y0 Q1 F5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
% k9 d4 ~+ U8 Q1 w2 t5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Two-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
9 I+ v8 {4 x$ C* v* U! V- ]Table of contents
5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
, n* u' G* D$ T7 k+ g6 l/ d. q5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7 T" |8 A7 M8 j, h; y: z5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
7 A low-power 16-bit three-step ADC for imaging applications 149

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