靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
& n7 s; L7 T: b7 W- ?0 p電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
4 [+ ]% i" C, O( K" y1 L儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
5 P+ r) {4 k6 ?& F* s- a9 D* c我的建議是去閎康，會比較適合。
因為我本身工作性質也是有接觸到ESD測試
1 E9 |( y; g* q* |3 h5 I測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
在Zap的次數明顯比軍歸來的少了。

ritafung

my company is pursuading to MIL-Std ...
! e1 ~4 m8 f6 Qactually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
& E+ Y6 [4 y  q* GThe following are the test combination:
1. Power to Power
( I, @/ I6 k3 E9 a2 U5 d" u9 M! S. S2. Power to Ground
( z9 r5 [7 Z! ]3 B- A3. IO to Power
- q5 Z0 N1 K. {; x, ^& v' F4. Io to Ground
5. IO to IO
: }! p# G, r/ K- D3 a4 a(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)
0 U# \  D7 A7 D% V$ J  ~/ U+ X
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
% S  F: B5 x) ]! W" R6 fFor example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
" a" W( e. L" @; {. jSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

For your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
' _9 X* A& ^* d2 q& ^+ E: H有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
  b& t8 [1 |% Q- c' E6 Xand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.