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AMD Geode LX 800@0.9W處理器
General Features
* A* r! w! k6 y& q, A% M■ Functional blocks include:% s/ t2 R+ X' T m$ W8 h. P
— CPU Core
. I1 a! l" H, i& ?— GeodeLink™ Control Processor! a. g3 `* J3 X& I+ \6 i5 a
— GeodeLink Interface Units
: ?! P9 [7 S& P1 P. @# C— GeodeLink Memory Controller
6 I( @( C# D! p2 b: ?— Graphics Processor4 M3 f$ A0 c5 T* d! q
— Display Controller- k& }" g% v2 F
— Video Processor
- n% P7 C6 ^' I1 c8 i2 i– TFT Controller/Video Output Port6 [% V7 Y0 f, z, _4 J$ _& p4 F" x
— Video Input Port
% |! Y. m8 t8 F, p! ^- |- Q$ L— GeodeLink PCI Bridge
, {" o8 P+ m" `& X— Security Block
1 p6 W/ ~& T- k4 p k% C■ 0.13 micron process
% `% T e4 s" {* T" J3 d& C■ Packaging:0 }+ k% ~* Y+ C5 D" [1 N- K
— 481-Terminal BGU (Ball Grid Array Cavity Up) with& M! O* k( s( Y- H3 c1 H. k
internal heatspreader$ I, a) [% U6 `' y; I
■ Single packaging option supports all features
& m3 h8 Q/ M2 ]+ n) @/ P5 \CPU Processor Features% U0 F& j& E ~5 h4 x7 i
■ x86/x87-compatible CPU core
y) Z# _" { |. ?) _9 I■ Performance:) u+ H2 J2 I" E4 K4 G" I
— Processor frequency: up to 500 MHz8 I5 x/ D3 z4 \' M! p2 p$ H) f
— Dhrystone 2.1 MIPs: 150 to 450
! s6 D4 n9 i: J0 A& h— Fully pipelined FPU, |( k1 N! Q) w
■ Split I/D cache/TLB (Translation Look-aside Buffer):
& G, ` Y7 u+ L/ C# _— 64 KB I-cache/64 KB D-cache: p* W. t7 O N' B
— 128 KB L2 cache configurable as I-cache, D-cache,
) u8 ^# ?. g% z" O% Por both
, f5 U! I* o; V, W! g■ Efficient prefetch and branch prediction
4 D7 a/ x* R4 B q# K8 U9 G, I0 x■ Integrated FPU that supports the MMX® and P) _2 e+ b$ Y3 A- M
AMD 3DNow!™ instruction sets
6 K0 w: s6 Y, T* b■ Fully pipelined single precision FPU hardware with
( [) a* x6 ?: \2 Amicrocode support for higher precisions
) J+ g! G5 t+ C! O% |GeodeLink™ Control Processor& F0 I0 _. @1 T# `3 j: {) ?3 L
■ JTAG interface:
; p! B% z; H6 w4 o( t' c v— ATPG, Full Scan, BIST on all arrays/ h* l* d2 ]4 g J; x! h v
— 1149.1 Boundary Scan compliant
7 V& S5 I" {0 p* b* ~- _■ ICE (in-circuit emulator) interface
2 r' y, Y/ |! r6 [■ Reset and clock control
) R N7 ]3 X4 b& n, R■ Designed for improved software debug methods and0 @/ R3 p( q" S
performance analysis5 S8 r" x7 B* h5 O* V
■ Power Management:9 `) x% C9 ~; w4 M; R% ~0 ~
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @, S+ w3 I, N# k5 l5 E
500 MHz max power3 _# x) ^7 u! Y/ N! k% c; y n: I
— GeodeLink active hardware power management
( W4 F0 q8 j5 Q( B9 d— Hardware support for standard ACPI software power/ c1 q* {4 S- Y2 Y8 ^
management) Z5 j/ ~: d7 O) r
— I/O companion SUSP/SUSPA power controls& W( m6 ?! Q# g& f/ [/ d3 V, Z" m9 E
— Lower power I/O
, M* ~) L5 J; [: Y+ i% Z2 \— Wakeup on SMI/INTR
2 l n: E5 ^ g, `■ Designed to work in conjunction with the! M$ a+ ^) T$ ~1 }% o4 a) U
AMD Geode™ CS5536 companion device
1 n! Z$ W7 P& P2 d0 }" g0 NGeodeLink™ Architecture6 [+ \ \7 q( |5 d1 b
■ High bandwidth packetized uni-directional bus for, v9 D; U: R( h
internal peripherals f9 ?7 ~1 f; h; A. a+ E3 i
■ Standardized protocol to allow variants of products to be; V8 ]# V- N( o4 B4 l
developed by adding or removing modules
% ?/ r- h% g* B w& m% S7 ]3 j■ GeodeLink Control Processor (GLCP) for diagnostics
2 G% E4 u4 O4 G3 I8 e( b$ L& y# Qand scan control
$ P- t: \7 l1 X' {( }1 N2 l5 d7 \- K5 v■ Dual GeodeLink Interface Units (GLIUs) for device interconnect6 m! \, N# L- Z1 c1 d% U t8 s
GeodeLink™ Memory Controller/ O. [3 Z v4 D+ R3 F4 W' y
■ Integrated memory controller for low latency to CPU and* V" _2 L" |0 E
on-chip peripherals& i8 M& L5 J" f% z4 ?
■ 64-bit wide DDR SDRAM bus operating frequency:! x+ P3 ]! d. S6 i
— 200 MHz, 400 MT/S+ D- _4 ?& E7 ^
■ Supports unbuffered DDR DIMMS using up to 1 GB
2 ]: t# m% L, ?DRAM technology& h! ^1 V n' w1 v# g+ H) R
■ Supports up to 2 DIMMS (16 devices max)
- a9 [' f! k$ v& \% A2D Graphics Processor2 `3 a7 c; F# h' c! w9 x) D& q
■ High performance 2D graphics controller
1 g; V/ `3 `5 f■ Alpha BLT. E7 N6 }/ ^+ l" ~6 s! k
■ Microsoft® Windows® GDI GUI acceleration:- e# t+ Z! } v" c9 I+ G
— Hardware support for all Microsoft RDP codes
6 j2 ~# [& l2 j, @* M5 A; r) I: `5 Y- O■ Command buffer interface for asynchronous BLTs
* J/ u$ B2 @# |- Q6 n■ Second pattern channel support
1 _# t* @6 K$ t7 U+ T) s■ Hardware screen rotation |
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