|
AMD Geode LX 800@0.9W處理器
General Features
4 p( u4 b, ]8 K @% u( B■ Functional blocks include:
% V2 v- }7 N! Y$ K— CPU Core2 h" A% K+ A% s8 @( D) [# I4 B: A; ~- R
— GeodeLink™ Control Processor# d: |/ B$ A; ?5 {$ E: k3 k9 J+ [
— GeodeLink Interface Units" v1 j% a: d4 }' ]
— GeodeLink Memory Controller2 y& E2 j0 A8 B- S8 `' b
— Graphics Processor( d( E) i+ f; M _9 P1 p
— Display Controller5 W8 l: R' p A
— Video Processor
* J% L2 b( w1 Z* v+ g– TFT Controller/Video Output Port5 [5 [5 t1 G( k3 r+ }$ j5 q; ?& l
— Video Input Port9 x2 Z6 ^) H4 [( _6 X. c* b
— GeodeLink PCI Bridge; _* r! ~; t) q* @+ ]: P2 B% I
— Security Block2 u) h2 h+ J2 c" u$ Q
■ 0.13 micron process6 H2 e# c; J/ K# V: Y6 w+ `' M5 T* P( s
■ Packaging:/ n! b( J/ V: \# | K
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
; {: y- Z/ Q% r! g+ {& i( Ointernal heatspreader+ C# q; D$ C- }6 x2 m
■ Single packaging option supports all features. K5 c% S1 W' p% D! E9 T6 I
CPU Processor Features" q. [9 J1 r! ? K5 x
■ x86/x87-compatible CPU core$ y ]3 L1 R( C7 z; w; K, e8 b' D8 d
■ Performance:
* d B. H" `. m/ i4 J2 I: h— Processor frequency: up to 500 MHz
' X0 T5 C: w& E6 C) s8 ~: E6 [+ ]— Dhrystone 2.1 MIPs: 150 to 450
& Q8 v. E, i% B) w% z1 M— Fully pipelined FPU
- [. K, ]1 V! ?$ q* R■ Split I/D cache/TLB (Translation Look-aside Buffer):' e7 @* K8 V+ g( D% I2 S
— 64 KB I-cache/64 KB D-cache
# i- T* D! S; e, ^— 128 KB L2 cache configurable as I-cache, D-cache,( k! T4 p1 N6 v6 e& H- w" Z
or both
' Y3 g3 I1 }& Y■ Efficient prefetch and branch prediction, G: k6 O9 c1 ~* v% c
■ Integrated FPU that supports the MMX® and
4 @' d* A( [& n' C# O% tAMD 3DNow!™ instruction sets) M) U( h: a% @) u; ]9 p
■ Fully pipelined single precision FPU hardware with3 `/ H3 d1 H. _; ?$ b; n
microcode support for higher precisions
. x9 |7 z: I0 f8 ?4 f) H& j. PGeodeLink™ Control Processor
) U2 r0 @. t t9 ]6 t9 Y# a7 w9 r■ JTAG interface:
% |2 H% T4 b' P0 v— ATPG, Full Scan, BIST on all arrays; \: Z# Y. k# x6 A# M- |! v
— 1149.1 Boundary Scan compliant) J- `7 X1 y% ?3 }
■ ICE (in-circuit emulator) interface( B, ^' c1 g, z/ l. X4 L* r2 |
■ Reset and clock control d& ~5 F# m5 n# w4 s- ~# B+ y W
■ Designed for improved software debug methods and* z' y5 f+ _3 I! u7 o. j& k$ E) c
performance analysis
9 p8 j2 B0 b; n* V: x■ Power Management:
3 G+ n% |4 I5 U! K- [, V% ^1 w— Total Dissipated Power (TDP) 3.8W, 1.6W typical @( f: X) Y m v, P: m
500 MHz max power% E& W5 w( ~' D
— GeodeLink active hardware power management
* S% A; p. R. ^) Z) P- h— Hardware support for standard ACPI software power
^. l/ Y2 Y7 q% h, C q' v/ D Z. }management
' V! Y8 ?- |$ \) s! n$ h1 D7 q— I/O companion SUSP/SUSPA power controls/ O2 k: ^7 t1 O5 z9 r1 m9 {5 `5 ~- g
— Lower power I/O. W: @; }3 R" f/ K
— Wakeup on SMI/INTR ^: S+ L( m/ H
■ Designed to work in conjunction with the
" d/ `8 e" [& x4 RAMD Geode™ CS5536 companion device
, S# H! R$ d s3 O) b0 UGeodeLink™ Architecture9 Y4 W6 F3 u' t3 M! E; ]
■ High bandwidth packetized uni-directional bus for
* s3 I1 N! U6 Y4 i6 finternal peripherals, p/ W$ \. Z X& y, v" F
■ Standardized protocol to allow variants of products to be7 [8 r8 s: n: X4 W# r: ~1 v9 R5 [
developed by adding or removing modules
! {$ v& a# t) i/ y+ a; r4 \■ GeodeLink Control Processor (GLCP) for diagnostics3 X$ \! D! c/ i: u' c" n: z
and scan control* C$ f/ G: z% w
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
, E3 V# s( a( z6 U& L9 ]6 wGeodeLink™ Memory Controller
" D. `7 {9 R2 G9 p% V, v■ Integrated memory controller for low latency to CPU and, Y+ M& @( q* R, f
on-chip peripherals8 v% O# T- d! K9 j3 ]4 v# M* C, F
■ 64-bit wide DDR SDRAM bus operating frequency:
0 t* J3 g% ]! v6 S. |8 T( I— 200 MHz, 400 MT/S* z7 j% ? H5 k) _( Y/ y
■ Supports unbuffered DDR DIMMS using up to 1 GB3 @2 h+ B% v6 H( B" C" j
DRAM technology
- Y% E1 G# n* `1 z+ s v■ Supports up to 2 DIMMS (16 devices max)
) c9 t+ }- H% A! |. F% e9 `9 F2D Graphics Processor4 j$ i1 L0 G1 v f: ?
■ High performance 2D graphics controller
8 k- [: Y5 t' a0 f( d* l8 L# ?■ Alpha BLT
+ \5 e2 r7 P5 e4 A■ Microsoft® Windows® GDI GUI acceleration:; F S' a! A- b9 p1 w" J* g% c
— Hardware support for all Microsoft RDP codes
U+ L2 K3 v, ?$ m8 \# O: M■ Command buffer interface for asynchronous BLTs4 [" G( S& b) S4 V
■ Second pattern channel support
* L4 L& k# w$ k+ U3 x8 k■ Hardware screen rotation |
|