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AMD Geode LX 800@0.9W處理器
General Features
3 L; Z$ C* f2 u0 I; r3 a■ Functional blocks include:
; d0 X0 E4 Z0 o3 z— CPU Core$ z+ I( I3 g6 L) L
— GeodeLink™ Control Processor
5 q+ ` P; z& n5 L7 i# d— GeodeLink Interface Units) C3 X, n: k6 \) m& t0 d
— GeodeLink Memory Controller
& W/ f6 V) T9 I6 b- x— Graphics Processor2 x+ a: F' ?! P; ~# r8 J% F
— Display Controller R m) m% _3 y! [
— Video Processor
' s& H- q) f/ h& ^ O6 `! m& o, ? Q– TFT Controller/Video Output Port
' K# B) C. R! e/ V7 H— Video Input Port% K8 e0 L( s0 t1 k: S. _! d
— GeodeLink PCI Bridge
, d) q7 q; z, S5 \" x— Security Block
# X2 S& D8 t8 a■ 0.13 micron process
7 W) C/ b6 ?% V$ b1 Q6 D■ Packaging:
- u* n' j+ w4 F/ Z— 481-Terminal BGU (Ball Grid Array Cavity Up) with1 H% m. F) M- e
internal heatspreader
9 B2 p y. e$ ?* i( r■ Single packaging option supports all features
. R* N4 b0 ^* |: `9 zCPU Processor Features5 k( o h9 O5 c9 s" J
■ x86/x87-compatible CPU core
0 r; \+ B4 M) \4 f8 h' z■ Performance:
: g8 @( U4 T6 C* u/ L— Processor frequency: up to 500 MHz
7 c% u, i. j, i1 G% U+ I+ A0 u— Dhrystone 2.1 MIPs: 150 to 450) `7 z! v9 Q0 b% @9 N; P; {
— Fully pipelined FPU
) l. K% F) p9 x# D■ Split I/D cache/TLB (Translation Look-aside Buffer):4 W# a' _2 d) V+ t$ a( H
— 64 KB I-cache/64 KB D-cache
( ]! ?2 T( \5 A8 D— 128 KB L2 cache configurable as I-cache, D-cache,
) o6 d+ X3 l r$ y3 ~4 y" s& x- Vor both
3 h: w& E2 N8 s( @& P■ Efficient prefetch and branch prediction
: \9 _, n9 {, @8 H■ Integrated FPU that supports the MMX® and
. c9 K0 D* D% q; a' J( ?AMD 3DNow!™ instruction sets. {3 h7 V7 ^; N
■ Fully pipelined single precision FPU hardware with
& y3 e9 X% q- Jmicrocode support for higher precisions
) I5 x, `. m B! p* pGeodeLink™ Control Processor
. ~1 y( W9 n- y■ JTAG interface:
) N2 Q8 |2 X3 `2 z- Q— ATPG, Full Scan, BIST on all arrays
4 h. R+ |# @' g+ y3 i @— 1149.1 Boundary Scan compliant0 M3 K1 M1 S" M
■ ICE (in-circuit emulator) interface+ b9 P, R; K J
■ Reset and clock control! [! y L1 @2 k3 m3 d, @4 y
■ Designed for improved software debug methods and
" h& J% i6 n x$ R$ G+ n3 Pperformance analysis& ?5 ]( x1 m; C" o8 i7 |9 l# r
■ Power Management:
: S; w! J W, ~3 I5 ?+ B$ l— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
' O9 X& l1 @ F; ^- c/ h- d, t500 MHz max power
$ v* I4 E5 y) u— GeodeLink active hardware power management
9 h5 f1 i7 f; L: Q7 P! i2 E' l— Hardware support for standard ACPI software power v' S! E" R( y) g6 F1 ~% N9 w: D
management+ |9 ^5 n' D4 O2 r, O/ l! d+ y9 ]" E
— I/O companion SUSP/SUSPA power controls
8 Q( V) i+ M5 x+ M( C— Lower power I/O- F" f) G* Z- e) M
— Wakeup on SMI/INTR1 \& E: B+ I& I: X
■ Designed to work in conjunction with the
: O, h( C) Z pAMD Geode™ CS5536 companion device% v2 }' z( O9 J. x# V/ t3 J
GeodeLink™ Architecture5 ~* k D+ t7 V' k- f& }! x) s
■ High bandwidth packetized uni-directional bus for/ P# A# f4 o9 R' [# [/ V( t% | K
internal peripherals
# p9 `- D, p9 N/ z+ b6 r1 R■ Standardized protocol to allow variants of products to be) x6 q8 \4 M% x0 W5 O9 d' k( b: Z
developed by adding or removing modules/ P6 F# ?' [5 V
■ GeodeLink Control Processor (GLCP) for diagnostics
T t5 c# f: iand scan control9 J% V, o( k4 T8 k& q6 u
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
! p- J4 ~$ y4 [2 @GeodeLink™ Memory Controller& {0 i& B% V( e( X# i( a
■ Integrated memory controller for low latency to CPU and
) g' `" L& n3 z" Q/ Son-chip peripherals
. s0 m0 R* {/ Q8 ^, Z■ 64-bit wide DDR SDRAM bus operating frequency:
' `8 L7 O7 r2 _3 w— 200 MHz, 400 MT/S$ s$ F) g# b. }" U( k# [
■ Supports unbuffered DDR DIMMS using up to 1 GB
; z2 }% Y R6 C" t) mDRAM technology
: B5 \0 c& U) N: I/ o■ Supports up to 2 DIMMS (16 devices max)
5 o+ L2 z! q% C6 g* m2 l2D Graphics Processor' c/ _6 A/ X o2 e! O& ^
■ High performance 2D graphics controller
t0 z2 L9 c+ i, a■ Alpha BLT
/ Z+ D# n4 t |■ Microsoft® Windows® GDI GUI acceleration:
/ s/ Z G1 h. }+ Q4 s, t— Hardware support for all Microsoft RDP codes& K- O0 k- c) D1 [- Q% @* ^2 H, p: ^
■ Command buffer interface for asynchronous BLTs
$ f3 J8 D' R) s5 p& Y■ Second pattern channel support
; W. t6 t2 T* t, V9 ]■ Hardware screen rotation |
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