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AMD Geode LX 800@0.9W處理器
General Features
/ p, @7 j e. \5 K" \8 x9 `6 N% m3 z■ Functional blocks include:
' j c {( V5 K$ s* ?9 {( g; u0 z— CPU Core( `1 S7 h8 M/ a' S
— GeodeLink™ Control Processor
& M% m8 k8 L$ w- R1 }3 h a— GeodeLink Interface Units, j$ c6 Q2 t5 Z# v6 _6 Q( x
— GeodeLink Memory Controller
" N5 q( U5 Q" O— Graphics Processor: A0 B" F+ D3 [1 P R7 n2 M# r
— Display Controller
. H% u! M7 A2 z8 m7 W/ Q3 L— Video Processor
. x7 H S4 }: W( Z– TFT Controller/Video Output Port# [1 M0 d, n, n; {# U
— Video Input Port
7 V$ L- U( K! `7 I# }— GeodeLink PCI Bridge
& O0 N o# I, }4 f9 m% O7 E' |— Security Block4 Y' ]1 X5 z, E+ L
■ 0.13 micron process' X8 z* }' x6 r0 O- F% C
■ Packaging:0 J0 d4 K8 Q* g0 @) o
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
+ ]2 a" ]$ I# |% v- z/ ~internal heatspreader" a! q- R$ H' @. [+ g
■ Single packaging option supports all features
" w+ [7 f2 }/ `. pCPU Processor Features& ~( i& d) e& S6 h. M8 ^
■ x86/x87-compatible CPU core
, \8 o F) ]! Y$ S6 U: q1 c■ Performance:
. N6 j; \+ G" O$ |% [- e— Processor frequency: up to 500 MHz
8 h. z4 i& V b— Dhrystone 2.1 MIPs: 150 to 450
, F' L3 I% r$ F. j( n- `! t+ a! c— Fully pipelined FPU. \4 A4 K# N6 R1 S& P' y( s; L, b
■ Split I/D cache/TLB (Translation Look-aside Buffer):
5 C& s- _% {9 p+ R1 [1 z— 64 KB I-cache/64 KB D-cache( T, E) u, s# w+ e; {0 O& C
— 128 KB L2 cache configurable as I-cache, D-cache,: ~, a c: s! B
or both
* G! ~6 h5 z% b1 l( ~* _: I■ Efficient prefetch and branch prediction' u7 j) ]) D) {; q$ K( G5 e
■ Integrated FPU that supports the MMX® and" u% y6 @ r- ?% X7 I
AMD 3DNow!™ instruction sets
! @% o" Y$ {" n■ Fully pipelined single precision FPU hardware with
. g; I) V4 n' }) i* ^0 w2 S, smicrocode support for higher precisions/ y. k( }" j) L. i. E
GeodeLink™ Control Processor0 f3 z r8 A" ^# K! o
■ JTAG interface:
+ `9 b% b* N) N5 B! _— ATPG, Full Scan, BIST on all arrays
& B+ y$ t7 D9 w. [/ Q9 B— 1149.1 Boundary Scan compliant, t& X% \/ \' u% [) e
■ ICE (in-circuit emulator) interface
- ^+ V/ Q7 L& I, y■ Reset and clock control
) a) r- f8 e% R- i) b( E+ L$ X■ Designed for improved software debug methods and3 k; G b/ W: @5 e' v+ _
performance analysis% W0 ^2 w$ }9 P z
■ Power Management:
) I8 C5 b' E1 T& h5 N— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
3 }- W% }! A+ l. @; U& `500 MHz max power
2 T6 x' \7 e! b: Z. e— GeodeLink active hardware power management
: {( |+ ~9 O0 W— Hardware support for standard ACPI software power* U! E9 U2 p! \: {& C; _$ d
management ~1 I m9 i5 T
— I/O companion SUSP/SUSPA power controls
|! m4 b; ~/ q5 o— Lower power I/O% y# C" Y! j- K3 H! W: x
— Wakeup on SMI/INTR
_" _9 ?0 T7 u% G# L■ Designed to work in conjunction with the
5 i9 E" d; z, @* G+ E' R: {AMD Geode™ CS5536 companion device( i* S0 V y# H; p$ f4 a" q/ x
GeodeLink™ Architecture9 O! [" O1 m" R# x0 m
■ High bandwidth packetized uni-directional bus for# N$ f- v2 g3 v" ~
internal peripherals+ R, G) e+ ]% h0 D/ m) i9 w
■ Standardized protocol to allow variants of products to be) D4 \' E. l0 V, Q
developed by adding or removing modules# ]; H% O6 x; d! `; D6 d8 v! a
■ GeodeLink Control Processor (GLCP) for diagnostics* W6 [& t5 B! R" T: k
and scan control
! {0 i. F. p8 x/ S■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
. S8 G# M! b5 ]) @- B) `5 k1 u1 C5 M) cGeodeLink™ Memory Controller" ~/ _ ] O# U! L e
■ Integrated memory controller for low latency to CPU and
6 l Y# t) Y$ N" H( d" Y7 son-chip peripherals
1 x5 R0 N5 C, e( r■ 64-bit wide DDR SDRAM bus operating frequency:/ U1 X5 A- x P4 x: z0 v
— 200 MHz, 400 MT/S
2 c) R/ ~9 \% G% I% e/ f■ Supports unbuffered DDR DIMMS using up to 1 GB) P: g! R! c3 y2 c3 a0 o
DRAM technology
8 G% a* x! a! c d4 N6 U& ~0 T■ Supports up to 2 DIMMS (16 devices max)
: U1 P& |1 z5 m. X6 ]# e/ r& ]2D Graphics Processor$ h+ k$ B/ c, c# k3 r$ ^
■ High performance 2D graphics controller, b9 Y8 p: E% i1 u$ I
■ Alpha BLT
+ s5 E( a0 L# A■ Microsoft® Windows® GDI GUI acceleration:
( Y3 f( N. |6 ]; r, S" c; j— Hardware support for all Microsoft RDP codes, \: E+ S0 c' a& N
■ Command buffer interface for asynchronous BLTs$ g: S7 J' W2 `
■ Second pattern channel support
* E9 O; [$ Y# f2 Z4 d■ Hardware screen rotation |
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