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AMD Geode LX 800@0.9W處理器
General Features& P$ h7 b0 ^4 R* B# {/ H& L1 P
■ Functional blocks include:
5 C, L9 Q; X" t: \7 X— CPU Core8 F) c9 U$ T8 o% q9 u/ c
— GeodeLink™ Control Processor
' {. h) O% ^7 t— GeodeLink Interface Units
: ~5 ~( q* r5 \& H— GeodeLink Memory Controller# [6 i, L9 r) {: I- [, K
— Graphics Processor% e; f( a$ O) g% h1 q. D* X
— Display Controller3 ]7 `/ P2 R3 V( a5 C1 K
— Video Processor
& p/ K: N+ ^" d- V$ ]* }– TFT Controller/Video Output Port" V9 B& N3 y! e, L+ e6 C
— Video Input Port9 c1 O5 H" ~+ W( A) Y/ j
— GeodeLink PCI Bridge0 H3 H$ W" w6 Y5 U( b5 [2 K
— Security Block
2 C- Z$ H9 K/ w: V■ 0.13 micron process H5 _5 y( x4 m/ M1 }
■ Packaging:1 ]& k2 M. h `
— 481-Terminal BGU (Ball Grid Array Cavity Up) with4 |+ q3 W3 r0 f, U7 s9 |) o8 Z# c
internal heatspreader2 J0 p# @! I4 d' F& ~, a
■ Single packaging option supports all features9 o. s. r. E( q* Q
CPU Processor Features" c: ^$ F( Z2 z: `) l3 }% h
■ x86/x87-compatible CPU core. |2 U8 R8 {) E3 ~5 w+ D6 S
■ Performance:' q; P- o* Q9 |! i2 j5 I
— Processor frequency: up to 500 MHz
, @/ N; y* e; v# g— Dhrystone 2.1 MIPs: 150 to 4509 Z( u* c4 s1 |0 {+ N
— Fully pipelined FPU7 v9 o% @5 k: D3 t8 o ]" z: z- z8 ~
■ Split I/D cache/TLB (Translation Look-aside Buffer):
& s7 l7 Y/ I8 D/ Q% o$ i! }3 v— 64 KB I-cache/64 KB D-cache
7 G. E5 H6 s! K$ R8 _— 128 KB L2 cache configurable as I-cache, D-cache,
" i& ^; m0 f" |+ h: t' aor both
, w$ x8 c; ~) m4 e" x5 g. I■ Efficient prefetch and branch prediction
1 ]' q: Q# [; U) Y+ \0 }■ Integrated FPU that supports the MMX® and
( I" N: [+ e. b( m% z8 P) z" ?AMD 3DNow!™ instruction sets J3 E: m/ b5 I
■ Fully pipelined single precision FPU hardware with
* |& A4 k+ `. `microcode support for higher precisions
+ Z+ O% j! ~3 T" hGeodeLink™ Control Processor0 ^" N$ c; U* |7 {
■ JTAG interface:$ R- q0 _4 H1 T; h! n8 ^
— ATPG, Full Scan, BIST on all arrays
4 N% C' y0 @9 u: ?! S— 1149.1 Boundary Scan compliant
9 ?$ C$ z* Y' T z4 _. M■ ICE (in-circuit emulator) interface6 J/ Y5 X' C2 B4 v( G
■ Reset and clock control
& {( }6 d; Q p* a6 P% B9 c■ Designed for improved software debug methods and
( ~9 L. U: G0 R! Dperformance analysis& h- x+ |5 T' Y
■ Power Management:* X- \! r0 m3 Q2 C: W7 A" i: H
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
( q% S; r" l) h2 ~# H500 MHz max power* E2 \( F7 D! k+ G8 x6 D
— GeodeLink active hardware power management
- t5 X* ]0 u* ^— Hardware support for standard ACPI software power6 f P* E% o0 f" z
management# |. B; n; r+ y1 U9 U4 J. R
— I/O companion SUSP/SUSPA power controls
- ?: w* ~' p6 w3 d/ Y, p— Lower power I/O& e% l ^7 ^4 C; j# e6 ~9 T$ {
— Wakeup on SMI/INTR" o$ r9 N0 Q; { {
■ Designed to work in conjunction with the
, s. P* a8 d( s, IAMD Geode™ CS5536 companion device
$ C+ ^. i* F. M- R, R# P& xGeodeLink™ Architecture, ]# p( y6 b$ w5 V. a$ M
■ High bandwidth packetized uni-directional bus for1 {* A0 {! R9 p- c3 X' J" Z& E
internal peripherals& Y: u" M% F0 x2 I( ?2 s/ c: ~
■ Standardized protocol to allow variants of products to be5 T' C6 g" _- ~3 u! J: V. u
developed by adding or removing modules
- c! X( Z1 e3 c' x4 s: o■ GeodeLink Control Processor (GLCP) for diagnostics
# C- J* P& p7 k4 ?and scan control- r: s6 F7 X1 v/ H" q2 X6 I& l
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect' B8 ]$ Y8 f; n2 \' R$ j8 I
GeodeLink™ Memory Controller- v" r" w5 f" v/ I, g. m+ Q
■ Integrated memory controller for low latency to CPU and
# A- l( R3 R: T( `' f8 yon-chip peripherals1 a2 t3 ]5 F- A& _$ [, Z* O
■ 64-bit wide DDR SDRAM bus operating frequency:
1 k/ T1 }+ ]% v5 n( |8 O0 @ q# y7 W— 200 MHz, 400 MT/S& g0 g( S$ {5 p% u, v' Y2 k9 \( S
■ Supports unbuffered DDR DIMMS using up to 1 GB
8 o; f) v7 u* Y0 Y- YDRAM technology7 z. T1 w+ F8 R+ V$ S# s
■ Supports up to 2 DIMMS (16 devices max)7 @5 C3 y0 r0 e+ C2 @
2D Graphics Processor. f' B- M' E3 y
■ High performance 2D graphics controller
$ i! E0 R" }9 h0 ?) r7 A- ]( h■ Alpha BLT
& K d6 x, l2 v6 C3 D& _+ i■ Microsoft® Windows® GDI GUI acceleration:9 r6 e. m5 K% m4 n: H7 t
— Hardware support for all Microsoft RDP codes
0 j& U7 E/ K( Q) E: E# h* T■ Command buffer interface for asynchronous BLTs
3 E( Q! k2 `! K6 X, W■ Second pattern channel support6 ~; `% V7 a) u5 o' F4 Z! R
■ Hardware screen rotation |
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