STD Cell Data Prepare 中 wire track 的問題?

hgby2209

Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack  
之後卻有如下之 Meaasge:
' S( D: h! D1 L. @0 H) |/ Y: o
) f% i4 v6 _9 X0 L/ s4 t******** Pin Access Analysis *******
** # Cell Masters    =  1000
1 O$ Z4 }3 O8 o! Z** # Ports (logical) = 2500
0 a! l# v/ F2 w& c, O: R6 K** # Pins (physical) = 2500
. a: B! e6 o( Q' Y* B/ h** # Pins with no good access point on Grid (V&H) =   5 ( 0%)
** # Pins with no good access point on Ver-Grid =    5 ( 0%)

4 h' q1 j4 u- `& ^% m* F請問下面這兩句是代表什麼意思呢?
6 t% a& s) K8 I. l# \1 E** # Pins with no good access point on Grid (V&H) =   5 ( 0%)
** # Pins with no good access point on Ver-Grid =    5 ( 0%)
5 Y' C1 [5 p, p4 c; u
2 ]7 J# V% ]5 u: ~: Y8 [7 R若是代表有錯誤的話是否要 Fix 呢?