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Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks! K, f0 g1 o4 `/ r: h
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack
6 m" Z. z8 R Z% C1 B6 c之後卻有如下之 Meaasge:
7 a% \8 I' _; j/ o1 R" G2 e% @+ n3 k; t
******** Pin Access Analysis *******
0 F* `$ ~ U5 U$ [" x5 Y** # Cell Masters = 1000
7 V4 e- K0 K$ v** # Ports (logical) = 2500
0 T3 Y9 ~2 }3 m3 A** # Pins (physical) = 2500% j7 i3 U+ G K$ C% ]
** # Pins with no good access point on Grid (V&H) = 5 ( 0%)
8 E, G1 T2 y9 Y** # Pins with no good access point on Ver-Grid = 5 ( 0%)9 Q6 e& }. b2 t- |
5 P) P4 g+ ~. \0 H請問下面這兩句是代表什麼意思呢?
7 v# E7 Y1 W0 ?! s! a' J+ Q** # Pins with no good access point on Grid (V&H) = 5 ( 0%)
* V r- Q. H& q" {** # Pins with no good access point on Ver-Grid = 5 ( 0%)
7 N ` M( \9 m3 Z : ?* P u! U$ ?6 r& T8 A1 k* O3 g! ]
若是代表有錯誤的話是否要 Fix 呢? |
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