Item
. |7 G7 m8 B2 W | SH77722 (SH-NaviJ2) Specifications0 M" e7 q! |. {' v3 x* b5 T
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Type name
0 }0 Y$ |$ z* h2 |$ c | R8A77722DA01BGV5 O t' V6 v% }# f& a" s0 }! M7 ?1 t& W
| R8A77722DA02BGV2 S: E3 C; b; O7 f
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Power supply voltage& i# J5 P0 r4 S: w& \
| 1.15 to 1.3 V (internal), 8 S% q2 ]/ t% V5 x! s
3.3 V and 1.8 V (external)
. y. y8 k9 ^. W) Y | 1.2 to 1.35 V (internal), ; p5 n; }& \: R
3.3 V and 1.8 V (external): S- ]1 X" p* F% L4 j4 u4 {
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Maximum operating frequency* n+ X# |$ Y& q0 \, q+ ^' s% ]
| 336 MHz& g- `7 }0 R0 T% r0 _
| 400 MHz
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Processing performance# ^( J- O4 |) N- T& J6 s- h2 ]
| 600MIPS, 2.3GFLOPS/ X3 n) q; b6 x z4 R6 q9 A
| 720MIPS, 2.8GFLOPS9 m: T- B& E5 h1 c0 q; L$ ^
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CPU core
) n; L$ {$ R9 h% r8 C# b% c$ f4 x. O | SH-4A core
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On-chip RAM8 n$ r1 o; L. A4 ?$ B
| ILRAM: 16 Kbytes& P% K6 [, n. b+ z
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Cache memory' ~4 Q/ G7 T! G8 {: j8 H
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory; w5 G( J8 A! H; `* u" _
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus
' [3 X) ]7 Z0 B( L2 \8 Q | DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus
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SRAM or ROM directly connected to extension bus# B% Y' @' i. X; s
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Extension bus+ r6 D: i; m/ A; b- X1 V) p9 {
| Address space: 64 Mbytes × 3% A3 I( Q9 o% W* e' w* k; [( V6 F
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Main on-chip peripheral functions
. f% g: h' m+ ?6 {) H1 t9 P- ~ | Renesas Graphics processor(2D/3D)3 o5 T8 x% L7 X- h
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Display control: outputs for two screens (digital RGB and LVDS)- L- b( q) C. M: o) M6 J
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Video input interface
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SD card host interface × 2 channels
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USB 2.0 host/function interface
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FM multiplex decoder% g/ B( B5 F: d9 n& _, O J4 A
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Controller area network (RCAN) interface × 2 channels
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MOST interface module% A6 q, h8 W/ j8 H
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Various audio interfaces × 4 channels6 N1 f/ s7 O1 g. O
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Dedicated DMAC × 26 channels+ `4 h2 Y* o7 E+ ?( X2 t
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I2C bus interface × 2 channels* ?* A9 k0 B( w/ a0 _" r8 K
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel
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A/D converter (10-bit) × 4 channels
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Timer × 9 channels
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On-chip debugging function
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Interrupt controller (INTC)1 l/ t+ P" R, s. A: G# q
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes" Y9 Y" V+ F, \* L$ Y
| Sleep mode* U1 c& g& Y7 x3 _+ q
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Module standby mode* E# _4 p Z5 ]0 W' z1 d7 \7 W
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DDR-SDRAM power supply backup mode
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Package
+ |) G$ G1 |+ Q2 P9 p | 449-pin BGA (21 mm × 21 mm)3 @ v1 R" K: ^
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